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FNF50560TD1 motion spm? 55 series october 2015 ?2015 fairchild semiconductor corporation 1 www.fairchildsemi.com FNF50560TD1 rev. 1.0 FNF50560TD1 motion spm ? 55 series features ? ul certified no. e209204 (ul1557) ? 600 v - 5 a 3-phase igbt inverter including control ic for gate drive and protections ? low-loss, short-circuit rated igbts ? built-in bootstrap diodes in hvic ? separate open-emitter pins from low-side igbts for three-phase current sensing ? active-high interface, works with 3.3 / 5 v logic, schmitt-trigger input ? hvic for gate driving, under-voltage and short-cir- cuit current protection ? fault output for under-voltage and short-circuit cur- rent protection ? inter-lock function to prevent short-circuit ? shut-down input ? hvic temperature-sensing built-in for temperature monitoring ? optimized for 15 - 20 khz switching frequency ? isolation rating: 1500 v rms / min. applications ? motion control - home appliance / industrial motor related resources ? an-9096 - smart power module, motion spm ? 55 series user?s guide ? an-9097 - spm ? 55 packing mounting guidance general description FNF50560TD1 is a motion spm 55 module providing a fully-featured, high-performanc e inverter output stage for ac induction, bldc, and pmsm motors. these modules integrate optimized gate drive of the built-in igbts to minimize emi and losses, while also providing multiple on-module protection features including under-voltage lockouts, inter-lock function, over-current shutdown, thermal monitoring of drive ic, and fault reporting. the built-in, high-speed hvic requires only a single supply voltage and translates the incoming logic-level gate inputs to the high-voltage, high-current drive signals required to properly drive the module's robust short- circuit-rated igbts. separate negative igbt terminals are available for each phase to support the widest variety of control algorithms. package marking and ordering inform ation figure 1. 3d package drawing (click to activate 3d content) device device marking package packing type quantity FNF50560TD1 FNF50560TD1 spmfa-a20 rail 13
FNF50560TD1 motion spm? 55 series ?2015 fairchild semiconductor corporation 2 www.fairchildsemi.com FNF50560TD1 rev. 1.0 integrated power functions ? 600 v - 5 a igbt inverter for three phase dc / ac power conversion (please refer to figure 3) integrated drive, protectio n and system control functions ? for inverter high-side igbts: gate drive circ uit, high-voltage isolated high-speed level shifting control circuit under-voltage lock-out (uvlo) protection ? for inverter low-side igbts: gate driv e circuit, short-circuit protection (scp) control supply circuit under-vol tage lock-out (uvlo) protection ? fault signaling: corresponding to uvlo (low-side supply) and sc faults ? input interface: high-active interface, wor ks with 3.3 / 5 v logic, schmitt trigger input ? built in bootstrap circuitry in hvic pin configuration figure 2. top view
FNF50560TD1 motion spm? 55 series ?2015 fairchild semiconductor corporation 3 www.fairchildsemi.com FNF50560TD1 rev. 1.0 pin descriptions pin number pin name pin description 1 p positive dc-link input 2u, v s (u) output for u phase 3v, v s (v) output for v phase 4w, v s (w) output for w phase 5n u negative dc-link input for u phase 6n v negative dc-link input for v phase 7n w negative dc-link input for w phase 8in (ul) signal input for low-side u phase 9in (uh) signal input for high- ide u phase 10 in (vl) signal input for low-side v phase 11 in (vh) signal input for high-side v phase 12 in (wl) signal input for low-side w phase 13 in (wh) signal input for high-side w phase 14 v dd common bias voltage for ic and igbts driving 15 com common supply ground 16 c sc capacitor (low-pass filter) for shor t-circuit current detection input 17 v f fault output, shut-down input, temperature output of drive ic 18 v b(w) high-side bias voltage for w-phase igbt driving 19 v b(v) high-side bias voltage for v-phase igbt driving 20 v b(u) high-side bias voltage for u-phase igbt driving
FNF50560TD1 motion spm? 55 series ?2015 fairchild semiconductor corporation 4 www.fairchildsemi.com FNF50560TD1 rev. 1.0 internal equivalent circ uit and input/output pins figure 3. internal block diagram note: 1. inverter high-side is composed of three igbts, freewheeling diodes, and one control ic for each igbt. 2. inverter low-side is composed of three igbts, freewheeling diodes, and one control ic for each igbt. it has gate drive and p rotection functions. 3. single drive ic has gate driver for six igbts and protection functions. 4. inverter power side is composed of four inverter dc-link input terminals and three inverter output terminals. vb ho hin lo vs lin csc v f com v dd csc v f in(wl) in(wh) v b(w) in(vh) v b(v) v b(u) in(uh) in(ul) nw nv nu u,vs (w) v,vs (v) u,vs (u) p in(vl) ho lo vs ho lo vs com vdd vb hin lin vb hin lin
FNF50560TD1 motion spm? 55 series ?2015 fairchild semiconductor corporation 5 www.fairchildsemi.com FNF50560TD1 rev. 1.0 absolute maximum ratings (t j = 25c, unless otherwise specified.) inverter part note: 5. the maximum junction temperature rating of the power chips integrated within the motion spm ? 55 product is 150 c. control part total system thermal resistance note: 6. for marking ? * ?, these value had been made an acquisition by the calculation considered to design factor. 7. for the measurement point of case temperature (t c ), please refer to figure 2. symbol parameter conditions rating unit v pn supply voltage applied between p - n u , n v , n w 450 v v pn(surge) supply voltage (surge) applied between p - n u , n v , n w 500 v v ces collector - emitter voltage 600 v * i c each igbt collector current t c = 25c, t j 150c 5 a * i cp each igbt collector current (peak) t c = 25c, t j 150c, under 1 ms pulse width 10 a * p c collector dissipation t c = 25c per chip 19 w t j operating junction temperature (note 5) -40 ~ 150 c symbol parameter conditions rating unit v dd control supply voltage applied between v dd - com 20 v v bs high-side control bias voltage applied between v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) 20 v v in input signal voltage applied between in (uh) , in (vh) , in (wh) , in (ul) , in (vl) , in (wl) - com -0.3 ~ v dd +0.3 v v f fault supply voltage applied between v f - com -0.3 ~ v dd +0.3 v * i f fault current sink current at v f pin 5 ma v sc current sensing input voltage applied between c sc - com -0.3 ~ v dd +0.3 v symbol parameter conditions rating unit v pn(prot) self protection supply voltage limit (short circuit protection capability) v dd = v bs = 13.5 ~ 16.5 v t j = 150c, non-repetitive, < 2 s 400 v t stg storage temperature -40 ~ 125 c v iso isolation voltage connect pins to heat sink plate ac 60 hz, sinusoidal, 1 minute 1500 v rms symbol parameter conditions min. typ. max. unit r th(j-c)q junction to case thermal resistance (note 7) inverter igbt part (per 1 / 6 module) - - 6.5 c / w r th(j-c)f inverter fwd part (per 1 / 6 module) - - 8.9 c / w
FNF50560TD1 motion spm? 55 series ?2015 fairchild semiconductor corporation 6 www.fairchildsemi.com FNF50560TD1 rev. 1.0 electrical characteristics (t j = 25c, unless otherwise specified.) inverter part note: 8. t on and t off include the propagation delay of the internal drive ic. t c(on) and t c(off) are the switching time of igbt itself under the given gate driving condition internally. for the detailed information, please see figure 4. figure 4. switching time definition symbol parameter conditions min. typ. max. unit v ce(sat) collector - emitter saturation voltage v dd = v bs = 15 v v in = 5 v i c = 4 a t j = 25c - 1.9 2.25 v t j = 150c - 2.4 - v v f fwdi forward voltage v in = 0 v i f = 4 a t j = 25c - 2.2 2.55 v t j = 150c - 2.0 - v hs t on switching times v pn = 400 v, v dd = v bs = 15 v, i c = 5a t j = 25c v in = 0 v ? 5 v, inductive load (note 8) 0.30 0.60 0.90 us t c(on) -0.150.35us t off -0.300.50us t c(off) -0.070.20us t rr -0.07- us ls t on v pn = 400 v, v dd = v bs = 15 v, i c = 5a t j = 25c v in = 0 v ? 5 v, inductive load (note 8) 0.30 0.60 0.90 us t c(on) -0.150.35us t off -0.300.50us t c(off) -0.070.20us t rr -0.07- us i ces collector - emitter leakage current v ce = v ces --1ma v ce i c v in t on t c(on) v in(on) 10% i c 10% v ce 90% i c 100% i c t rr 100% i c v ce i c v in t off t c(off) v in(off) 10% v ce 10% i c (a) turn-on (b) turn-off
FNF50560TD1 motion spm? 55 series ?2015 fairchild semiconductor corporation 7 www.fairchildsemi.com FNF50560TD1 rev. 1.0 control part note: 9. short-circuit protection is functioning for all six igbts. figure. 5. v-t curve of temperature output of ic (5v pull-up with 10kohm) symbol parameter conditions min. typ. max. unit i qdd quiescent v dd supply current v dd = 15 v, in (uh,vh,wh,ul,vl,wl) = 0 v v dd - com - 1.5 2.0 ma i pdd operating v dd supply current v dd = 15 v, f pwm = 20 khz, duty = 50%, applied to one pwm signal input v dd - com - 2.0 2.5 ma i qbs quiescent v bs supply current v bs = 15 v, in (uh, vh, wh) = 0 v v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) -3060 a i pbs operating v bs supply current v dd = v bs = 15 v, f pwm = 20 khz, duty = 50%, applied to one pwm signal input for high - side v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) - 500 650 a v fh fault output voltage v sc = 0 v, v f circuit: 10 k to 5 v pull-up 4.5 - - v v fl v sc = 1 v, v f circuit: 10 k to 5 v pull-up - - 0.5 v v sc(ref) short-circuit trip level v dd = 15 v (note 4) 0.45 0.5 0.55 v uv ddd supply circuit under-voltage protection detection level 10.7 11.4 12.1 v uv ddr reset level 11.2 12.3 13.0 v uv bsd detection level 10.1 10.8 11.5 v uv bsr reset level 10.7 11.4 12.1 v i ft hvic temperature sensing current v dd = v bs = 15 v, t hvic = 25c 688195 a v ft hvic temperature sensing voltage v dd = v bs = 15 v, t hvic = 25c, 10 k to 5 v pull-up (figure. 5) 4.05 4.19 4.32 v t fod fault-out pulse width 40 120 - s v fsdr shut-down reset level applied between v f - com - - 2.4 v v fsds shut-down set level 0.8 - - v v in(on) on threshold voltage applied between in (uh) , in (vh) , in (wh) , in (ul) , in (vl) , in (wl) - com --2.4v v in(off) off threshold voltage 0.8 - - v 0255075100125 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v f [v] t hvic [ o c]
FNF50560TD1 motion spm? 55 series ?2015 fairchild semiconductor corporation 8 www.fairchildsemi.com FNF50560TD1 rev. 1.0 bootstrap diode part figure 6. built-in bootstrap diode charatersts recommended oper ating conditions note: 10. this product might not make response if input pulse width is less than the recommanded value. note: 11. rc coupling at each input (parts shown dotted) might change depending on the pwm control scheme used in the application and the wiring impedance of the application?s printed circuit board. the input signal section of the spm 55 product integrates 10 k ( typ.) pull-down resistor. therefore, when using an external filtering resistor, please pay attention to the signal voltage drop at input terminal. figure 7. recommended mcu i/o interface circuit symbol parameter conditions min. typ. max. unit r bs bootstrap diode resitance v dd = 15v, t c = 25c - 280 - symbol parameter conditions min. typ. max. unit v pn supply voltage applied between p - n u , n v , n w - 300 400 v v dd control supply voltage applied between v dd - com 14.0 15 16.5 v v bs high - side bias voltage applied between v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) 13.0 15 18.5 v dv dd / dt, dv bs / dt control supply variation -1 - 1 v / s t dead blanking time for preventing arm - short for each input signal 0.5 - - s f pwm pwm input signal - 40 c t j 150c - - 20 khz v sen voltage for current sensing applied between n u , n v , n w - com (including surge voltage) -4 4 v p win(on) minimun input pulse width (note 10) 0.7 - - s p win(off) 0.7 - - 0123456789101112131415 0.00 0.01 0.02 0.03 0.04 0.05 0.06 i f [a] v f [v] t j =25 o c, v dd =15v mcu com 5 v line (mcu or control power) ,, in (u l) in (vl) in (w l) ,, in (uh ) in (vh ) in (w h ) v f r pf = 10k ? spm
FNF50560TD1 motion spm? 55 series ?2015 fairchild semiconductor corporation 9 www.fairchildsemi.com FNF50560TD1 rev. 1.0 mechanical characteristics and ratings figure 8. flatness measurement position figure 9. mounting screws torque order note: 12. do not make over torque when mounting screws. much mounting torque may cause package cracks, as well as bolts and al heat-s ink destruction. 13. avoid one side tightening stress. figure 10 shows the recommended torque order for mounting screws. uneven mounting can cau se the ceramic substrate of the motion spm 55 product to be damaged. the pre-screwing torque is set to 20 ~ 30 % of maximum torque rating. parameter conditions min. typ. max. unit device flatness see figure 8 -50 - 100 m mounting torque mounting screw: - m3 note figure 9 recommended 0.7 n ? m 0.6 0.7 0.8 n ? m recommended 7.1 kg ? cm 5.9 6.9 7.9 kg ? cm weight -6.0- g
FNF50560TD1 motion spm? 55 series ?2015 fairchild semiconductor corporation 10 www.fairchildsemi.com FNF50560TD1 rev. 1.0 time charts of protective function a1 : control supply voltage rises: after the voltage rises uv ddr , the circuits start to operate when next input is applied. a2 : normal operation: igbt on and carrying current. a3 : under voltage detection (uv ddd ). a4 : igbt off in spite of control input condition. a5 : fault output operation starts. a6 : under voltage reset (uv ddr ). a7 : normal operation: igbt on and carrying current. figure 10. under-voltage protection (low-side) b1 : control supply voltage rises: after the voltage reaches uv bsr , the circuits start to operate when next input is applied. b2 : normal operation: igbt on and carrying current. b3 : under voltage detection (uv bsd ). b4 : igbt off in spite of control input c ondition, but there is no fault output signal. b5 : under voltage reset (uv bsr ) b6 : normal operation: igbt on and carrying current figure 11. under-voltage protection (high-side) (with the external shunt resistance and cr connection) input signal output current fault output signal control supply voltage reset uv ddr protection circuit state set reset uv ddd a1 a3 a2 a4 a6 a5 a7 input signal output current fault output signal control supply voltage reset uv bsr protection circuit state set reset uv bsd b1 b3 b2 b4 b6 b5 high-level (no fault output)
FNF50560TD1 motion spm? 55 series ?2015 fairchild semiconductor corporation 11 www.fairchildsemi.com FNF50560TD1 rev. 1.0 d1 : high side first - input - first - output mode d2 : low side noise mode : no lo d3 : high side noise mode : no ho d4 : low side first - input - first - output mode d5 : in - phase mode : no ho figure 12. inter-lock function hin : high-side input signal lin : low-side input signal ho : high-side output signal lo : low-side output signal csc : short-circuit current detection input vf : fault out function figure 13. fault-out function by over current protection hin lin ho lo /fo hin : high-side input signal lin : low-side input signal ho : high-side igbt gate voltage lo : low-side igbt gate voltage /fo : fault output d1 d2 d3 d4 d5 hin lin ho lo csc vf no output activated by next input after fault clear o ver-c urrent detection soft off smart turn-off
FNF50560TD1 motion spm? 55 series ?2015 fairchild semiconductor corporation 12 www.fairchildsemi.com FNF50560TD1 rev. 1.0 hin : high-side input signal lin : low-side input signal ho : high-side output signal lo : low-side output signal csc : over current detection input vf : shutdown input function figure 14. shutdown input function by external command hin lin ho lo csc vf no output activated by next input after fault claear external shutdown input soft o ff smart turn-off
FNF50560TD1 motion spm? 55 series ?2015 fairchild semiconductor corporation 13 www.fairchildsemi.com FNF50560TD1 rev. 1.0 note: 1) to avoid malfunction, the wiring of each input should be as short as possible. (less than 2 ~ 3 cm) 2) by virtue of integrating an applicatio n specific type of hvic inside the spm ? 55 product, direct coupling to mcu terminals without any opto-coupler or transformer isolation is possible. 3) v f is open-drain type. this signal line should be pulled up to the positive side of the mcu or control power supply with a resist or that makes i fo up to 5 ma. please refer to fig- ure 15. 4) c sp15 of around seven times larger than bootstrap capacitor c bs is recommended. 5) input signal is active-h igh type. there is a 10 k resistor inside the ic to pull down each input signal line to gnd. rc coupling circuits is recommanded for the prevention of input signal oscillation. r s c ps time constant should be selected in the range 50 ~ 150 ns . ( recommended r s = 100 ? , c ps = 1 nf) 6) to prevent errors of the protection function, the wiring around r f and c sc should be as short as possible. 7) in the short-circuit protection circuit, please select the r f c sc time constant in the range 1.5 ~ 2 s. 8) the connection between control gnd line and power gnd line which includes the n u , n v , n w must be connected to only one point. please do not connect the control gnd to the power gnd by the broad pattern. also, the wiring distance between control gnd and power gnd should be as short as possib le. 9) each capacitor should be mounted as close to th e pins of the motion spm 55 product as possible. 10) to prevent surge destruction, the wiring between the smoothing capacitor and the p and gnd pins should be as short as possi ble. the use of a high frequency non-inductive capacitor of around 0.1 ~ 0.22 f between the p and gnd pins is recommended. 11) relays are used at almost every systems of electrical equipmen ts of home appliances. in these cases, there should be suffi cient distance between the cpu and the relays. 12) the zener diode or transient voltage suppressor should be adopted for the protection of ics from the surge destruction betw een each pair of control supply terminals. (recommanded zener diode is 22 v / 1 w, which has the lower zener impedance characteristic than about 15 ? ) 13) please choose the electrolytic capacitor with good temperature characteristic in c bs . also, choose 0.1 ~ 0.2 f r-category ceramic capacitors with good temperature and frequency characteristics in c bsc . 14) for the detailed information, please refer to the application notes. figur15. typical application circuit fault 15v line c bs c bsc c sp15 c spc15 r pf c bpf r s m v dc c dcs gating uh gating vh gating wh gating ul gating vl gating wl c pf m c u r sw r sv r su u-phase current v-phase current w-phase current r f n w (7) n v (6) n u (5) w (4) v (3) u (2) p (1) (20) v b(u) (19) v b(v) (16) c sc (17) v f (8) in (ul) (10) in (vl) (12) in (wl) (9) in (uh) (11) in (vh) (18) v b(w) (14) v dd (13) in (wh) input signal for short-circuit protection c sc r s r s r s r s r s r s c ps c ps c ps c ps c ps c ps in(wh) in(vh) in(uh) com vdd vs(v) vs(u) vs(w) vb(u) vb(v) vb(w) (15) com out(wh) out(vh) out(uh) temp. monitoring 5v line c spc05 c sp05 c bs c bsc c bs c bsc in(wl) in(vl) in(ul) vf csc out(wl) out(vl) out(ul)
FNF50560TD1 motion spm? 55 series ?2015 fairchild semiconductor corporation 14 www.fairchildsemi.com FNF50560TD1 rev. 1.0 detailed package outline drawi ngs (FNF50560TD1, short lead)
?2015 fairchild semiconductor corporation www.fairchildsemi.com

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